The present invention relates generally to an address configuration technique for asynchronous transfer mode (ATM) switched networks, and specifically to a method of configuring nodes in an ATM switched network after power-up or a return from an inactive condition.
Asynchronous transfer mode (ATM) offers an advantageous transport structure for digital communications. ATM provides a high-bandwidth, multiplexing scheme for packet-based transmission of messages. In ATM, information to be communicated is packaged in fixed-size cells of relatively short length. Each cell contains a 5-octet label called a header that identifies the cell and the cell's connections. A 48-octet payload follows the header in the ATM cell and carries user information intended for a recipient. Switching networks rely on information stored in the header of ATM cells to switch and multiplex the cells along appropriate routes.
Endpoints in an ATM switched network are commonly referred to as nodes. Generally, a node may comprise a circuit board having electronics for transmitting, receiving, and processing information carried within the payload of the ATM cells. A switched ATM network will include a plurality of nodes, which typically are circuit boards or modules, connected together via an ATM switch. The ATM switch establishes virtual connections between itself and each of the nodes. The virtual connections are point-to-point between the ATM switch and the nodes, such that one node can communicate with another node in the ATM network only by way of the ATM switch.
For ATM cells to reach a desired destination, that destination must have a known ATM address. Conventionally, each node has a dedicated hardware address set by a non-volatile mechanism at the time of its manufacture or installation. For example, each circuit card in a rack of circuit cards that are nodes in an ATM switched network may contain non-volatile memory that stores a unique address for that node. If the node fails and must be replaced, maintenance personnel must then program the replacement node, or module, with the unique address for the node. Alternatively, the circuit card may have its unique address set by a physical switch or similar device. In this instance, maintenance personnel must physically configure a replacement node with the appropriate unique address prior to its installation.
When a node is replaced in the ATM switched network and powers-up, the replacement node conventionally broadcasts its hardware address on the ATM switched network. An address server linked to the ATM network has stored the hardware addresses of the nodes in the network, and will recognize the hardware address broadcast by the replacement node. Subsequently, the address server will assign a network address to the replacement node, and the replacement node will be able to communicate within the ATM switched network.
A problem may arise when a large number of nodes are first installed or become active in the network, such as after a power-up condition. In this instance, the installed or reactivated nodes will simultaneously broadcast their hardware addresses to the network address server and expect to receive their network addresses. Detrimental and unnecessary congestion on the ATM switched network may result.
Moreover, the unique hardware addresses for nodes in an ATM switched network increase the cost of manufacturing and maintaining the network. Customizing each node with a physical mechanism adds to the expense of manufacture and decreases the ease of interchangeability between circuit cards. Also, customizing each node by programming non-volatile memory adds to the time for replacing a failed node, which may be critical to the continued availability of the ATM switched network.
In light of the foregoing, a need exists for a technique to address a replacement node in an ATM switched network without requiring specialized manufacturing or installation activity to individually configure the node prior to its installation. A need also exists for a technique to avoid unnecessary congestion to an ATM network address server caused by the broadcasting of hardware addresses by a plurality of individual nodes upon power-up of the ATM network.